During the manufacture of semiconductor memories, such as a synchronous dynamic random access memories ("SDRAMs"), it is necessary to test each memory cell to ensure it is operating properly. Electronic and computer systems containing semiconductor memories also normally test the memories when power is initially applied to the system. A typical SDRAM includes a number of arrays, each array including a number of memory cells arranged in rows and columns. During testing of the SDRAM, each memory cell must be tested to ensure it is operating properly. To test the memory cells, a memory tester applies address, data, and control signals to the SDRAM to write data to and read data from all the memory cells in the arrays. In a typical prior art test method, data having a first binary value (e.g, a "1") is written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a "0") is typically written to and read from the memory cells. The memory tester determines a memory cell is defective when the data written to the memory cell does not equal the data read from the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern 101010 . . . written to the memory cells in each row of the array.
As the storage capacity of SDRAMs increases, the number of data transfers performed in testing every memory cell increases accordingly. Each data transfer requires a bus cycle, and the greater the number of bus cycles the greater the time and thus the cost of testing the SDRAM. Data compression has been used in some SDRAMs to reduce the number of bus cycles required to test the memory cells. FIG. 1 is a block diagram of a portion of a conventional SDRAM 10 including conventional test data compression circuits 12 and 14. The SDRAM 10 includes first and second memory banks 15a and 15b including two groups of arrays 16-22 and 36-42, respectively, each array including a plurality of memory cells (not shown in FIG. 1) arranged in rows and columns, as known in the art. In memory bank 15a, a plurality of sense amplifier circuits 24-34 are coupled to the arrays 16-22. The sense amplifier circuits 24-34 sense and store the data contained in activated memory cells in the associated one of the arrays 16-22, as understood by one skilled in the art. The memory bank 15b similarly includes sense amplifier circuits 44-54 coupled to the arrays 36-42. The SDRAM 10 includes two data terminals DQ0 and DQ1 physically located adjacent the memory bank 15a. The test data compression circuit 12 is coupled between the data terminal DQ0 and the sense amplifier circuits 24-34 in memory bank 15a. More specifically, the test data compression circuit 12 is coupled to each of the sense amplifier circuits 24-34 through test data read lines 56 and test data write lines 58. In the same way, the test data compression circuit 14 is coupled to the sense amplifier circuits 44-54 of memory bank 15b through test data read lines 60 and test data write lines 62.
In operation during testing of the SDRAM 10, a memory tester (not shown in FIG. 1) places the SDRAM 10 in a test mode of operation. In the test mode, the test data compression circuits 12 and 14 each operate in two modes, a test data write mode and a test data read mode. In the test data write mode, the test data compression circuit 12 transfers test data placed on the data terminal DQ0 across the test data write lines 58 and through the corresponding sense amplifier circuits to activated memory cells in the arrays 16-22. For example, if the arrays 16 and 20 are active, the test data placed on the data terminal DQ0 is transferred through the appropriate one of the sense amplifier circuits 24 and 26 to an activated memory cell in the array 16, and is simultaneously transferred through the appropriate one of the sense amplifier circuits 30 and 32 to an activated memory cell in the array 20. The test data compression circuit 14 operates in the same way to transfer test data placed on the data terminal DQ1 over the test data write line 62 to the activated memory cells in the arrays 36-42.
In the test data read mode, the test data compression circuit 12 receives test data placed on the test data read lines 56 from activated memory cells in the arrays 16-22. If the arrays 16 and 20 are active, data stored in an accessed memory cell in array 16 and an accessed cell in array 20 is transferred over the test data read lines 56 to the compression circuit 12. The test data compression circuit 12 compares the test data on the test data read lines 56 and places an error signal on the data terminal DQ0 indicating the result of that comparison. Typically, the same binary value is written to all memory cells during the test data write mode, and the error signal indicates if any of the activated memory cells stores a different binary value. The circuit 14 operates in the same way to compare data stored in bank 15b and place and error signal on the terminal DQ1. The memory tester monitors the states of the error signals on the data terminals DQ0 and DQ1 to detect defective memory cells in the memory banks 15a and 15b, respectively.
If the memory tester detects a defective memory cell, the row of memory cells containing the defective cell is replaced using redundant rows of memory cells contained in the SDRAM 10, as understood by those skilled in the art. When using data compression, however, the precise memory cell that is defective is not immediately known by the memory tester. For example, if the active memory cells are in the arrays 16 and 20 and one of these active memory cells is defective, the test data compression circuit 12 drives the error signal on the data terminal DQ0 to a level telling the memory tester that one, but not which one, of the activated memory cells is defective. In order to determine which of the arrays 16 and 20 contains the defective memory cell, the memory tester must perform additional tests on the cells. Such additional testing may include individually writing data to and reading data from the memory cells to determine which of the two is defective.
Additional testing by the memory tester adds to the time and thus the expense of testing the SDRAM 10, and is accordingly undesirable. As a result, it is typically advantageous to simply replace rows in both arrays when a defective memory cell is detected. Although this increases the number of redundant rows needed in the SDRAM 10, the reduced test time and resulting cost savings typically outweigh additional space required for the additional redundant rows. The data from too many arrays cannot be compressed, however, or else the advantages of reduced testing time are outweighed by the extra rows unnecessarily replaced in the additional arrays.
In order to avoid unnecessarily utilizing redundant rows of memory cells, the memory banks 15a and 15b are partitioned by defining "redundancy planes" within and between the memory banks. A redundancy plane defines a group of arrays having their data compressed together. For example, in memory bank 15a the dotted line 64 defines a redundancy plane between the arrays 16,20 and 18,22, and in memory bank 15b the dotted line 66 defines a redundancy plane between the arrays 36,40 and 38,42. The redundancy plane defined by the dotted line 64 indicates that the data from the arrays 16 and 20 will be compressed together, and the data from the arrays 18 and 22 will likewise be compressed together. The data from arrays on opposite sides of a redundancy plane, such as arrays 16 and 18, are not compressed together. In this way, the number of arrays having their data compressed is limited to the number of arrays within a particular redundancy plane. In the SDRAM 10, the redundancy planes defined by the dotted lines 64 and 66 are naturally defined due to the sharing of the sense amplifier circuits by the arrays in each row, as understood by one skilled in the art. A redundancy plane indicated by the dotted line 68 is also defined between the memory banks 15a and 15b. Once again, this means that data from the memory bank 15a is not compressed with data from the memory bank 15b. Thus, a defective memory cell in one of the arrays in memory bank 15a does not result in rows being replaced in any of the arrays in the memory bank 15b.
In order to partition the SDRAM 10 into the desired redundancy planes, the routing of the test data read lines 56,60 and test data write lines 58,62 may become difficult. This is particularly true of the so called "H-Architecture" depicted in FIG. 1, where the line 68 corresponds to the horizontal member of the "H" and each row of arrays corresponds to a vertical member of the "H." In the H-Architecture, the data terminals DQ are typically positioned adjacent the arrays in one of the banks as shown. As a result, the length of the lines 56-62 connecting the data terminals DQ and the arrays may become undesirably long. For example, as the number of arrays in each row increases the length of the lines 56,58 between the circuit 12 the arrays in the upper row of bank 15a becomes longer, as do the lines 60,62 coupled between the circuit 14 and the arrays in bank 15b. In addition, the routing of the lines 56-62 may become increasingly difficult as the density of the SDRAM 10 increases due to reduced spaces in which to position such lines. Furthermore, as more arrays are added to the memory banks 15a and 15b, the electrical characteristics of the test data read lines 56,60 and test data write lines 58,62 may differ substantially from those of the normal test data read and test data write paths. This is undesirable because the electrical characteristics of the SDRAM 10 in the test mode are ideally the same as those when operating in the normal mode in order to perform reliable testing of the SDRAM 10.
There is a need for a test circuit having simplified test data read and test data write paths for testing memory cells in an SDRAM.